The invention relates to programmable logic devices (PLDs). More particularly, the invention relates to a lookup table for a PLD that includes transistors having more than one oxide thickness.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBS) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure.
More advanced FPGAs can include more than one type of logic block in the array. For example, the Xilinx Virtex-II Pro(trademark) FPGA includes blocks of Random Access Memory (RAM), blocks implementing multiplier functions, and embedded processor blocks. (The Xilinx Virtex-II Pro FPGA is described in detail in pages 19-71 of the xe2x80x9cVirtex-II Pro Platform FPGA Handbookxe2x80x9d, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FPGA CLBS typically include several xe2x80x9clookup tablesxe2x80x9d (LUTs). A LUT is an addressable memory array that is typically loaded with data during the configuration process. For example, a Virtex-II Pro CLB includes eight LUTS. Each LUT has four data input terminals that address the configurable memory. By storing predetermined values in the appropriate memory locations, the LUT can be configured to provide any function of up to four variables.
FIG. 1 shows a typical LUT structure 100, which includes 16 memory locations (configuration memory cells M0-M15) addressed by four input signals IN0-IN3. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The output of each memory cell passes through two pass transistors, one of transistors T0-T15 followed by one of transistors U0-U7. Transistors T0-T15 are controlled by LUT input signal IN0 and its inverse (provided by inverter I0), while transistors U0-U7 are controlled by LUT input signal IN1 and its inverse (provided by inverter I1). After passing through these two transistors, the signals from the memory cells have been narrowed down to four signals on internal nodes INT8-INT11.
Each internal node INT8-INT11 drives a corresponding buffer 101a-101d. The output signals from buffers 101a-101d are again passed through two transistors, one of transistors V0-V3 followed by one of transistors W0-W1. Transistors V0-V3 are controlled by LUT input signal IN2 and its inverse (provided by inverter I2), while transistors W0-W1 are controlled by LUT input signal IN3 and its inverse (provided by inverter I3). The one remaining signal (on internal node INT14) is passed through another buffer 102 to provide the LUT output signal OUT. Thus, by controlling the four pass transistors on each path between the memory cells and the LUT, and by configuring the memory cells to store the desired values, any function of up to four variables can be implemented.
FIG. 1A shows a simplified configuration memory cell Mx that can be used to implement memory cells M0-M15 of FIG. 1. Configuration memory cell Mx can include, for example, a pair of cross-coupled inverters A, B, with two pass transistors d1, d2 that allow the configuration logic (not shown) to access the memory cell. Configuration memory cells are well known in the art of FPGA design, therefore, detailed exemplary descriptions are not included herein.
FIG. 1B illustrates one well-known implementation 101x of buffer 101. Buffer 101x includes two inverters coupled in series. The first inverter includes P-channel transistor P1 (the pullup) and N-channel transistor N1 (the pulldown), coupled in series between power high VDD and ground GND. Optional second inverter I4 can increase the performance of the buffer and ensures that the buffer output signal has the same sense as the buffer input signal. P-channel transistor P2 is driven by the node N between the two inverters, and acts to pull node INT up to VDD such that pullup P1 is fully turned off. Optional P-channel transistor P3 is used to initialize node INT to a high value, for example during reset or power-up of the FPGA. Buffer 102 can be the same as buffer 10x, can omit the initialization pullup, or can be a simple inverter or some other well-known buffer circuit.
The structure shown in FIG. 1 works well at sufficiently high values of VDD (power high, or the operating voltage of the FPGA). For example, for many years VDD was standardized at 5 volts (5 V), plus or minus ten percent (10%). (The ten percent allowable variation was included in the specifications of each device to allow for normal deviations in manufacturing and operation.) However, operating voltages are being steadily reduced both to save power and to meet the requirements of smaller and smaller transistors. For example, a transistor with a thinner oxide layer breaks down at a lower gate voltage than a transistor with a thicker oxide layer. Thus, values of VDD have been reduced to 2.5 V, then 1.8 V, and even as low as 1.5 V. A VDD value of 1.2 V is now contemplated, and at these low voltage levels the structure of FIG. 1 is no longer adequate, as is now described in conjunction with FIG. 2.
When a high value is passed through an N-channel transistor, the voltage is reduced by Vt, the threshold voltage level of the N-channel transistor. (For purposes of simplifying the present discussion, other well-known transistor effects such as the body effect are not described.) For example, FIG. 2 shows an input signal IN passing through transistor T (which is driven by VDD) to internal node INT. Internal node INT drives buffer 201, which provides the output signal OUT. When input signal IN is at the same voltage level as VDD, the voltage at internal node INT is the gate voltage reduced by one threshold voltage (VINT=VDDxe2x88x92Vt).
This well-known limitation presents no problem when VDD=5 V, as described above. When processes supporting this operating voltage are used, the N-channel threshold voltage is less than one volt (1 V). Thus, the voltage at internal node INT is still more than four volts (4 V), which is quite sufficient to turn on the N-channel pulldown N1, thus turning on P-channel pullup P2 in buffer 201 (see FIG. 1B). However, at sufficiently low levels of VDD, the voltage at internal node INT is so low as to impair the performance of the circuit.
For example, if node INT does not rise sufficiently high, the N-channel pulldown in buffer 201 might not be completely on, and the P-channel pullup P2 might not be sufficiently on to quickly turn off pullup P1. Thus, the pullup (e.g., pullup P1) xe2x80x9cfightsxe2x80x9d the pulldown (e.g., pulldown N1), and slows down the switching of the output node. For example, referring again to FIG. 1B, while P-channel transistor P2 helps in raising node INT to VDD once node N goes low, transistor P2 is no help if node N does not go low enough to turn it on.
As described, there is a voltage drop when a high voltage is passed across an N-channel transistor. However, there is no corresponding voltage drop of a high voltage across a P-channel transistor. Therefore, one solution to this problem is to replace the N-channel transistor with paired N- and P-channel transistors, with the P-channel transistors being driven by the complementary input signal. However, this solution can double the size of the lookup table by doubling the number of pass transistors. Further, both the true and complement signals must be provided to the paired transistors, which increases the die area. Larger buffers must also be provided to handle the increased load of driving both the N- and P-channel transistors.
Another way to accommodate lower VDD levels is to drive the gates of the N-channel transistors with a voltage level VGG higher than VDD, as shown in FIG. 3 and Table 1. In this case, the voltage level after passing a high value VDD through the N-channel transistor T is the gate voltage VGG minus the N-channel threshold voltage Vt, or VINT=VGGxe2x88x92Vt. Voltage level VGG is often specified for an FPGA, where VGG is the maximum voltage that can safely be applied to the gate of a transistor in the device. The VGG voltage level is at least partially determined by the oxide thickness of the transistor. Generally speaking, the thicker the layer of oxide over the transistor, the higher the voltage level that can be applied to the gate without damaging the transistor. Additionally, the longer the gate length (channel length) of the transistor, the less leakage current (i.e., off state current) occurs across the transistor from source to drain. Therefore, up to an intrinsic limit, the longer the gate length, the higher the voltage level that can be applied across the source and drain of the transistor without producing an unacceptably high leakage current.
However, FPGA manufacturers are not only reducing operating voltage levels on their devices, but are also reducing minimum feature sizes to lower costs. Sometimes, each new product generation uses a lower operating voltage and has reduced feature sizes. Reduced feature sizes mean thinner oxide and shorter gate lengths. Therefore, specified values of VGG are being rapidly reduced. For example, Table 1 shows the relationships between various exemplary values of VDD (the operating voltage), VGG (the maximum allowable gate voltage), Vt (the N-channel threshold voltage), and VINT (the voltage at node INT). Also included are typical gate lengths for each manufacturing process. All of the values shown in Table 1 are merely exemplary, as they vary between processes and manufacturers. VDD values are specified as nominal operating voltages.
Note that as VGG approaches twice the threshold voltage (VGG=2Vt), the voltage at node INT becomes insufficient to adequately turn on pulldown N1 (see FIG. 1B). Therefore, it is desirable to provide alternative structures for implementing lookup tables in FPGAs that can accommodate a lower operating voltage and smaller feature sizes than known structures. It is further desirable to provide circuits having the same characteristics that can be used for any purpose in FPGAs or other integrated circuits.
The invention provides a structure that can be used, for example, to implement a lookup table (LUT) for a programmable logic device (PLD). The structure includes transistors of varying oxide thickness, operating voltage, and, in some embodiments, gate length.
The structure includes a plurality of configuration memory cells, a first plurality of pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, which provides a buffer output signal. In some embodiments, the buffer output signal is the output signal for the structure. Some embodiments include more than one such buffer, and the buffer output signals are passed through at least a second plurality of pass transistors to an output buffer, which provides the output signal for the structure.
The pass transistors are controlled by the data input signals of the structure. The pass transistors have a first oxide thickness and the data input signals are provided at a first operating voltage. The memory cells and buffer(s) include transistors having a second oxide thickness thinner than the first oxide thickness, and,operate at a second operating voltage lower than the first operating voltage. In some embodiments, the second operating voltage is the operating voltage used as a supply voltage by a majority of the transistors in the PLD.
Some embodiments include data generating circuits (e.g., inverters, level shifters, input multiplexers, and so forth) that provide the signals controlling the pass transistors. Because these circuits provide signals at the first operating voltage, they include transistors having the first oxide thickness.
In some embodiments, the gate length also varies between the memory cell transistors, pass transistors, buffer transistors, and data generating circuit transistors. To support the higher operating voltage with acceptable leakage, the data generating circuits have the longest gate length. The memory cell transistors and buffer transistors, on the other hand, operate at the lower voltage (with thinner oxide) and can have the shortest gate length without generating unacceptable leakage current. The pass transistors are gated by the higher voltage and thus require the thicker oxide. However, the drain-to-source voltage for the pass transistors is less than the higher operating voltage, so the gate length of the pass transistors can be somewhere between the longest and shortest gate lengths without generating unacceptable leakage current.
In other embodiments, the data generating circuits and pass transistors have a first and longer gate length, while the memory cell transistors and buffer transistors have a second and shorter gate length. In yet other embodiments, the gate lengths are the same for the data generating circuits, pass transistors, memory cell transistors, and buffer transistors.
According to some embodiments, a circuit includes a plurality of memory cells, an internal node, a plurality of pass transistors coupled between the plurality of memory cells and the internal node, and a buffer coupled between the internal node and an output terminal. Each pass transistor has a gate terminal coupled to receive from a data input terminal a selected one of a ground signal and a power high signal at a first voltage level. Each pass transistor has a first oxide thickness. Each memory cell is coupled to an operating voltage at a second voltage level less than the first voltage level. Each memory cell includes memory cell transistors having a second oxide thickness, where the second oxide thickness is less than the first oxide thickness. The buffer is coupled to an operating voltage at the second voltage level. The buffer includes buffer transistors having the second oxide thickness.
In some embodiments, the circuit is a lookup table (LUT) structure in an FPGA. In other embodiments, the circuit forms a portion of a PLD other than an FPGA, such as a Complex Programmable Logic Device, (CPLD), or a fuse or antifuse device, for example. In other embodiments, the circuit forms a portion of a non-programmable IC.
According to some embodiments, an FPGA includes an interconnect structure, a plurality of input multiplexers coupled to the interconnect structure and to an operating voltage at a first voltage level, and a plurality of LUT structures coupled to the input multiplexers. Each of the LUT structures includes a plurality of memory cells, an internal node, an output terminal coupled to the interconnect structure, a plurality of data input terminals each coupled to an output terminal of one of the input multiplexers, a plurality of pass transistors coupled between the memory cells and the internal node, and a buffer coupled between the internal node and the output terminal.
Each pass transistor has a gate terminal coupled to receive from a data input terminal a selected one of a ground signal and a power high signal at the first voltage level. Each pass transistor has a first oxide thickness. Each memory cell is coupled to an operating voltage at a second voltage level less than the first voltage level, and includes memory cell transistors having a second oxide thickness, where the second oxide thickness is less than the first oxide thickness. The buffer is coupled to an operating voltage at the second voltage level, and includes buffer transistors having the second oxide thickness. Each input multiplexer includes input multiplexer transistors having the first oxide thickness.
In some embodiments, each LUT structure includes additional pass transistors and buffers, and the buffer is coupled to the output terminal through the additional pass transistors and buffers.
In some embodiments, the FPGA includes input/output blocks coupled to the interconnect structure. Each input/output block includes input/output transistors having a third oxide thickness greater than the first oxide thickness. Thus, the FPGA includes transistors having three different oxide thicknesses.
According to some embodiments, an integrated circuit device (IC) includes a plurality of input/output blocks, a plurality of interconnect lines coupled to the input/output blocks; and a circuit coupled to the interconnect lines. The circuit includes a plurality of memory cells, an internal node, an output terminal coupled to one of the interconnect lines, a data generating circuit coupled to the interconnect lines and to an operating voltage at a first voltage level, a plurality of pass transistors coupled between the memory cells and the internal node, and a buffer coupled between the internal node and the output terminal.
Each pass transistor has a gate terminal coupled to receive from the data generating circuit a selected one of a ground signal and a power high signal at a first voltage level. The data generating circuit includes data generating transistors having a first oxide thickness. Each pass transistor has the first oxide thickness. Each memory cell is coupled to an operating voltage at a second voltage level less than the first voltage level. Each memory cell includes memory cell transistors having a second oxide thickness, where the second oxide thickness is less than the first oxide thickness. The buffer is coupled to an operating voltage at the second voltage level. The buffer includes buffer transistors having the second oxide thickness.
In some embodiments, the input/output blocks each comprise input/output transistors having a third oxide thickness greater than the first oxide thickness.
According to some embodiments, a circuit includes a plurality of first input terminals, an internal node, a plurality of pass transistors coupled between the first input terminals and the internal node, and a buffer coupled between the internal node and an output terminal. Each pass transistor has a gate terminal coupled to receive from a data input terminal a selected one of a ground signal and a power high signal at a first voltage level. Each pass transistor has a first oxide thickness. Each first input terminal is coupled to provide a selected one of the ground signal and a power high signal at a second voltage level less than the first voltage level. The buffer is coupled to an operating voltage at the second voltage level. The buffer includes buffer transistors having a second oxide thickness, where the second oxide thickness is less than the first oxide thickness.